High speed serial links operating at over 3 gigabits per second (Gbs) over distances in excess of several feet using only copper traces on conventional FR-4 dielectric printed circuit board (PCB) electrical backplanes have become commonplace. In fact, transceivers operating at rates in excess of 6 Gbs over similar PCB-based serial links are now becoming available in the marketplace. It is expected that rates of 10 Gbs will soon be introduced.
Such serial links commonly employ a serializer/deserializer (SERDES) at each end for multiplexing and demultiplexing multiple, M-ary pulse amplitude modulated (M-PAM) non-return-to-zero (NRZ) high speed data streams. As the bit rates (and concomitant frequencies) have escalated over time, system designers have had to contend with the difficulty of communicating over these increasingly dispersive links without sacrificing system performance. As bit rates increase, intersymbol interference (ISI) and noise caused by crosstalk from other signals on the PCB increases. The signal-to-noise ratio (SNR) decreases due to the ISI and the noise to the point that discerning the boundary between adjacent received symbols at the receiver end becomes quite difficult. As a result, recovering a clock signal may become difficult, and bit error rates (BER) may rise to an unacceptable level as a result.
An oscilloscope trace of the serial link at the receiver end reveals overlapping, phase-shifted M-PAM NRZ waveforms with intermittent gaps, colloquially called “data eyes,” between the waveforms. The dimensions of each data eye, both horizontal (time) and vertical (voltage), diminish as dispersion increases and collapse at the extreme. To recover clock and data signals from the symbols correctly, the SERDES should accurately track the waveforms in terms of both time and voltage. The best opportunity to do this occurs by operating in the center of data eye, where adjacent symbols are best discriminated from one another.
The current trend in SERDES design is to gravitate toward techniques more commonly encountered in digital communications system design: increased reliance on signal processing and statistical system characterization. One of the more prominent examples of this design philosophy is evident in the application of channel equalization to combat the increased frequency selectivity of the channel. Proper channel equalization maximizes the effective dimensions of the data eye, affording the SERDES the best chance of interpreting symbols correctly.
It is important to determine that new SERDES designs and systems incorporating such SERDES designs are working optimally. Proper equalizer performance evaluation dictates that both the horizontal and vertical dimensions of the recovered data eye be measured and compared against expected operating conditions, including the recovered clock location in the data eye and the voltage sensitivity of the receiver. Misequalization problems can thus be corrected before the designs are put into production. In addition, SERDES and system margins can be measured during operation.
The typical technique for evaluating the performance of a SERDES is to scan the data eye to find its boundaries by varying the offset voltage and clock signal phase at which the SERDES is sampling the incoming waveforms. The boundary of the data eye is encountered when the BER rises to a threshold level. Unfortunately, this technique is of no use whatsoever if a SERDES is equipped with an equalizer that is a decision feedback equalizer (DFE).
The DFE (see, Austin, “Decision-Feedback Equalization for Digital Communication Over Dispersive Channels,” MIT Lincoln Laboratory, Tech. Report No. 437, August 1967, incorporated herein by reference) has become very popular in communications system design due to its effectiveness under a wide variety of channel types. The DFE is a nonlinear equalizer and is especially effective on channels with severe dispersion, because it can correct for channel imperfections without displaying the excessive noise enhancement of a linear equalizer. A DFE has a precursor (or feedforward) equalizer and a postcursor (or feedback) equalizer. The precursor equalizer is a linear transversal filter, the purpose of which is to cancel precursor ISI. The precursor equalizer does this by filtering the channel output, attempting to relocate most of the channel precursor energy to the postcursor response of the filtered output.
The postcursor equalizer is strictly causal. The postcursor equalizer uses past decisions to cancel the remaining postcursor ISI from the current decision variable. Unfortunately, because the postcursor equalizer bases subsequent decisions on earlier decisions, the varying of offset voltage and clock signal phase that occurs when scanning the data eye confuses the DFE; an incorrect symbol decision degrades subsequent symbols. The result is an inaccurate assessment of the SERDES's performance. In addition, the timing of the feedback decisions is critical in a DFE, especially at high data rates. This prevents the arbitrary movement of the clock position within the data eye.
What is needed in the art is a more generally applicable way to test equalizer-based SERDES. More specifically, what is needed in the art is a way to test DFE-based SERDES. Even more specifically, since many SERDES are now embodied in integrated circuits (ICs), what is needed in the art is a way to test DFE-based SERDES ICs with relatively few architectural changes or little additional hardware.